About Sangun Choi
I am a 4th year Ph.D student at Korea University. My research interest lies in broad topics for improving the energy efficiency of computing systems, including neural processing unit (NPU) architectures, graphics processing unit (GPU) architectures, and memory systems of future datacenter servers.
I'm focusing on developing an energy-efficient on-chip memory system for NPUs. NPUs implement their on-chip memory systems primarily with SRAM, consuming over 40% of the total chip area. Despite this substantial silicon investment, existing systems fail to utilize these memory resources energy-efficiently. Therefore, they necessitate a novel on-chip memory system design and management technique that offers a sustainable scalability and adaptability to diverse characteristics of emerging workloads.
Please check our publications for more details!
Research Interests
- Sustainable NPU Architecture
- Future Memory Systems
- Software Techniques for GPUs
Publications
- HALO: Hybrid Systolic Arrays via Logical Partitioning for Acceleration of Complex-Valued Neural Networks (IISWC 2025, Co-Author)
- MOST: Memory Oversubscription-aware Scheduling for Tensor Migration on GPU Unified Storage (IEEE CAL, Co-Author)
- Kubism: Disassembling and Reassembling K-Means Clustering for Mobile Heterogeneous Platforms (LCTES 2025, First Author)
- TM-Training: An Energy-Efficient Tiered Memory System for Deep Learning Training in NPUs (ACM TOS, Co-Author)
- TLP Balancer: Predictive Thread Allocation for Multi-Tenant Inference in Embedded GPUs (IEEE ESL, Co-Author)
- SAVector: Vectored Systolic Arrays (IEEE Access, First Author)