About Sangun Choi

I am a fifth-year Ph.D. candidate at Korea University. My research interests broadly encompass improving the energy efficiency of computing systems, including neural processing unit (NPU) architectures, graphics processing unit (GPU) architectures, and memory systems for future datacenter servers.

My current work focuses on developing energy-efficient on-chip memory systems for NPUs. NPUs implement their on-chip memory predominantly with SRAM, which occupies over 40% of the total chip area. Despite this substantial silicon investment, existing systems fall short of utilizing these memory resources in an energy-efficient manner. This challenge motivates the need for novel on-chip memory designs and management techniques that offer sustainable scalability and adaptability to the diverse characteristics of emerging workloads.

Please refer to our publications for more details.

Publications

IEEE CAL EONSim: An NPU Simulator for On-Chip Memory and Embedding Vector Operations (First Author)

IEEE TC Bauhaus: Restructuring Vector Database for LLM Retrieval on CXL-Based Tiered Memory (Co-Author)

IISWC HALO: Hybrid Systolic Arrays via Logical Partitioning for Acceleration of Complex-Valued Neural Networks (Co-Author)

IEEE CAL MOST: Memory Oversubscription-aware Scheduling for Tensor Migration on GPU Unified Storage (Co-Author)

LCTES Kubism: Disassembling and Reassembling K-Means Clustering for Mobile Heterogeneous Platforms (First Author)

ACM TOS TM-Training: An Energy-Efficient Tiered Memory System for Deep Learning Training in NPUs (Co-Author)

IEEE ESL TLP Balancer: Predictive Thread Allocation for Multi-Tenant Inference in Embedded GPUs (Co-Author)

IEEE Access SAVector: Vectored Systolic Arrays (First Author)

Useful Links

LinkedIn GitHub Google Scholar Lab Page